In radiofrequency (RF) applications, different types of structures may be used for making RF components.
Among these structures, HR-SOI (acronym for “High-Resistivity Silicon-On-Insulator”) type substrates are of interest.
In the present text, “high resistivity” means an electrical resistivity of more than 500 Ohm cm.
A Silicon-On-Insulator (SOI) structure comprises successively a silicon base substrate, a dielectric (e.g., oxide) layer (usually called “buried oxide” (BOX) layer), and a silicon active layer.
To improve the insertion loss, harmonic distortion and isolation performance required for Radiofrequency (RF) switches, the silicon base substrate of an SOI substrate was replaced by a high-resistivity base substrate in order to form an HR-SOI.
The adoption of HR-SOI wafers for RF applications has allowed monolithic integration of RF front-end modules. This leads to smaller size, better reliability, improved performance and lower system cost.
While HR-SOI substrates are well suited for 2G and 3G applications, they suffer from the parasitic surface conduction (PSC) layer induced under the buried oxide due to fixed oxide charges, which attract free carriers near the Si/SiO2 interface.
This drastically reduces the substrate effective resistivity by more than one order of magnitude, limiting the substrate capability in meeting performance requirements for next generation devices.
To address this intrinsic limitation and improve effective resistivity, a polycrystalline silicon layer may be introduced between the dielectric layer and the high resistivity base substrate to provide a trap-rich layer underneath the dielectric layer and impede the PSC.
These traps originate from the grain boundaries of the polycrystalline silicon layer in which RF components are to be made.
Reference can be made to document WO 2012/127006.
FIG. 1 shows an enhanced HR-SOI structure that comprises an HR silicon substrate 1, covered successively by a polycrystalline silicon (also called “polysilicon”) layer 2′, an oxide layer 4 and a monocrystalline silicon layer 3 that forms the active layer of the substrate 1.
Such an enhanced HR-SOI structure can be made by the SMART CUT® process, which comprises the following steps:                providing an HR silicon substrate,        depositing a polycrystalline silicon layer on the HR silicon substrate,        providing a monocrystalline silicon donor substrate comprising a weakened zone that defines the active layer to be transferred onto the HR silicon substrate; the weakened zone can be obtained by implantation of atomic species into the donor substrate,        forming a dielectric layer on at least one of the polycrystalline silicon substrate and the monocrystalline donor substrate, e.g., by oxidizing at least one of the substrates,        bonding the donor substrate and the HR silicon substrate, at least one dielectric layer being at the bonding interface; the at least one dielectric layer forms the BOX layer,        detaching the donor substrate along the weakened zone, thereby transferring the monocrystalline active layer onto the HR silicon substrate.        
The enhanced HR-SOI structure resulting from this process includes residual electrical charges at the interface between the BOX layer and the underlying layer that are due to the implantation and oxidation steps.
The electrical charges deteriorate the RF performance of the components that are later formed in or on the active layer. In particular, the electrical charges may create undesirable interactions between adjacent RF components.
The polycrystalline silicon layer is intended to trap the electrical charges and thus avoid their detrimental effect on the RF performance. Indeed, the surface of the polycrystalline silicon layer comprises a plurality of grain boundaries which allow trapping of the electrical charges at the interface with the BOX layer.
Further information on this subject can be found in publications written by D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., pp. 46-47, 2004; D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer and J.-P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate,” IEEE Transactions on Electron Devices, vol. 55, no. 7, pp. 1664-1671, 2008; and D. C. Kerr et al., “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer,” 978-1-4244-1856-5/08, IEEE 2008.
However, the manufacturing of such an HR-SOI structure involves some steps carried out at high temperature (e.g., a heat treatment is carried out after bonding in order to reinforce the bonding strength). The high temperature induces recrystallization of the polycrystalline silicon layer, the underlying HR silicon substrate—which is monocrystalline—acting as a seed for such recrystallization. In other words, a recrystallization front propagates through the polysilicon layer from the interface with the HR monocrystalline silicon substrate.
When recrystallizing, the polysilicon layer loses its trapping efficiency due to the drop in the number of grain boundaries and larger grain size variation which could result in larger surface roughness and charge trapping uniformity.
In order to limit recrystallization, the thickness of the polysilicon layer can be set to a sufficiently high thickness such that, at the end of the high temperature step(s), at least a part of the polysilicon layer has not recrystallized yet.
Besides, a large deposited thickness is also needed to compensate the fact that the polysilicon layer has to be polished after deposition in order to reduce its roughness, the polishing step removing a certain thickness of the polysilicon layer.
For these reasons, in current-enhanced HR-SOI structures, the deposited polysilicon layer typically has a thickness thicker than 2 μm.
However, increasing the thickness of the polysilicon layer has a drawback. Indeed, when the polysilicon layer is deposited using chemical vapor deposition (CVD), the polysilicon first forms nuclei on the surface of the HR silicon substrate, and then forms small grains that progressively enlarge in a substantially conical way as the thickness of the polysilicon layer grows. As a result, the surface of the polysilicon layer opposite to the HR silicon substrate comprises less grain boundaries than the surface located at the interface with the HR silicon substrate. Hence, the greater the thickness of the polysilicon layer, the smaller the number of grain boundaries and, thus, the lower the trapping efficiency of the polysilicon layer.